Electrical Engineering - Digital System
Exam Duration: 45 Mins Total Questions : 30
If the number of bits in input and output codes is 4 and 8 respectively for a ROM. The memory of this chip equals to
- (a)
12 bit
- (b)
32 bit
- (c)
128 bit
- (d)
256 bit
For the circuit shown, the counter state (Q1,Q0) follow the sequence
- (a)
00,01,10,11,00
- (b)
01,10,00,01
- (c)
00,01,11,00,01
- (d)
10,11,00,10
The initial state of MOD-16 down counter is 0110. What will it be after 37 clock pulses?
- (a)
Intermediate
- (b)
0101
- (c)
0001
- (d)
0110
A 4 bit D/A converter gives an output voltage of 4.5 V for an input code of 1001. The output voltage for an input code of 0110 is
- (a)
1.5 V
- (b)
2.0 V
- (c)
3.0 V
- (d)
4.5 V
8-bit A/D converter, the quantization error is given by (in per cent)
- (a)
0.392
- (b)
0.521
- (c)
0.212
- (d)
0.425
In an 8 bit D/A converter, the reference voltage used is 10 V. What voltage is represented by 10100001 ?
- (a)
0.00392 V
- (b)
6.314 V
- (c)
6.288 V
- (d)
0.00391 V
An 8 bit digital ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with VT =6 mV. What will be the digital output to Va = 6 V?
- (a)
100110111
- (b)
100111001
- (c)
11001010
- (d)
10111010
A 4 bit modulo-6 ripple counter usesJ-K flip-flop. If the propagation delay of each flip-flop is 70 ns, the maximum clock frequency that can be used is equal to
- (a)
3.1 MHz
- (b)
3.6 MHz
- (c)
4.2 MHz
- (d)
4.9 MHz
Which of the following is the truth table of the given logic?
- (a)
x y z 0 0 0 0 1 1 1 0 1 1 1 1 - (b)
x y z 0 0 1 0 1 1 1 0 1 1 1 1 - (c)
x y z 0 0 1 0 1 0 1 0 0 1 1 0 - (d)
x y z 0 0 0 0 1 1 1 0 1 1 1 0
The characteristics equation of the T flip-flop is given by
- (a)
\({ Q }^{ + }=T\overline { Q } +Q\overline { T } \)
- (b)
\({ Q }^{ + }=\overline { T } Q+T\overline { Q } \)
- (c)
\({ Q }^{ + }=TQ\)
- (d)
\({ Q }^{ + }=T\overline { Q } \)
If a counter having 10 flip-flops initially at 0, what count will it hold after 2060 pulses?
- (a)
000 000 1110
- (b)
000 001 1100
- (c)
000 001 1000
- (d)
000 000 1100
To convert any counter into count down, the gate that can be used is
- (a)
XNOR
- (b)
AND
- (c)
XOR
- (d)
OR
The following circuit represents
- (a)
\(W=\overline { AB+C } +DA\)
- (b)
\(W=AB+B\overline { C } +ACD\)
- (c)
\(W=A(B+CD)BC\)
- (d)
None of the above
The complete set of only those logic gates designed as universal gates is
- (a)
NOT, OR and AND gates
- (b)
XNOR, NOR and NAND gates
- (c)
NOR and NAND gates
- (d)
XOR, NOR and NAND gates
An 8 bit successive approximation A/D converter has a full-scale reading of 2.55 V and its conversion time for an analog input of 1 V is 20\(\mu s\) . The conversion time for a 2 V input will be
- (a)
10 \(\mu s\)
- (b)
20 \(\mu s\)
- (c)
40 \(\mu s\)
- (d)
50 \(\mu s\)
If the minimum output voltage of a 7 bit D/A is 25.4 V. What is the smallest change in the output as the binary count increase?
- (a)
0.2 V
- (b)
0.5 V
- (c)
25.9 V
- (d)
0.1 V
Counter shown below is supplied with a constant clock frequency of fc , then output \(\overline { { Q }_{ 0 } } ,\overline { { Q }_{ 1 } } ,\overline { { Q }_{ 2 } } \) will have frequency of
- (a)
fc/8
- (b)
f c/6
- (c)
f c/3
- (d)
Data is insufficient
Borrow (B) of full subtractor is represented by following logic function, where X is MSB input bit and Z is LSB input bit
- (a)
\(Y\overline { \left( X\bigoplus Y \right) } Z+X\overline { Y } \)
- (b)
\(Y\left( X\bigoplus Y \right) Z+\overline { XY } \)
- (c)
\(Y\overline { \left( X\bigoplus Y \right) } Z+\overline { X } Y\)
- (d)
\(\overline { \left( X\bigoplus Y \right) } Z+\overline { X } Y\)
The shift register shown in the figure is initially loaded with the bit pattern 1010. Subsequently, the shift register is clocked and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position (MSB). After how many clock pulses will the content of the shift register become 1010 again?
- (a)
3
- (b)
7
- (c)
11
- (d)
15
A digital circuit, which compares two numbers \({ A }_{ 3 }{ A }_{ 2 }{ A }_{ 1 }{ A }_{ 0 },{ B }_{ 3 }{ B }_{ 2 }{ B }_{ 1 }{ B }_{ 0 }\) is shown in figure. To get output Y=0, choose one pair of correct input numbers.
- (a)
1010,1010
- (b)
0101,0101
- (c)
0010,0010
- (d)
0010,1011
If X1 and X2 are the inputs to the circuits shown in figure, the output Q is
- (a)
\(\overline { { X }_{ 1 }+{ X }_{ 2 } } \)
- (b)
\(\overline { { X }_{ 1 }{ X }_{ 2 } } \)
- (c)
\(\overline { { X }_{ 1 } } { X }_{ 2 }\)
- (d)
\({ X }_{ 1 }{ X }_{ 2 }\)
Statement 1 The dynamic memories have lower packing density than static memories.
Statement 2 Dark current is the phenomenon related to static memories.
Of these statements which option is correct?
- (a)
1-True, 2-False
- (b)
1-True; 2-True
- (c)
1-False; 2-True
- (d)
1-False; 2-False
For a 8 bit D/A converter used to produce analog signal which controls speed of DC motor rated till 100 rpm speed, the number of steps required to reach speed of 40 rpm is equal to
- (a)
6
- (b)
115
- (c)
102
- (d)
7
The 4 bit 2's complement representation of a decimal number is 1000. The number is
- (a)
+8
- (b)
zero
- (c)
-7
- (d)
-8
The number of product terms in the minimized sum of products expression obtained through the following K-map is (where, x denotes don't care states
1 | 0 | 0 | 1 |
0 | \(\times \) | 0 | 0 |
0 | 0 | \(\times \) | 1 |
1 | 0 | 0 | 1 |
- (a)
2
- (b)
3
- (c)
4
- (d)
5
In the circuit shown, the input bits 0 and 1 are represented by 0 and 5 V respectively. The op-amp is ideal but all the resistances and the 5 V inputs have tolerance of ± 10%. The specification- for the tolerance of DAC is
- (a)
10%
- (b)
25%
- (c)
35%
- (d)
5%
A 4-bit right shift register is initialized to value 1000 for (Q3 ,Q2 , Q1 Q0)· The D input is derived from Q0 , Q2 and Q3 through two XOR gates as shown in figure. The pattern 1000 will appear at
- (a)
3 rd pulse
- (b)
7th pulse
- (c)
6th pulse
- (d)
4th pulse
In the following circuit, X is given by
- (a)
\(X=A\overline { B } \overline { C } +\overline { A } B\overline { C } +\overline { A } \overline { B } C+ABC\)
- (b)
\(X=\overline { A } BC+A\overline { B } C+AB\overline { C } +\overline { A } \overline { B } \overline { C } \)
- (c)
X=AB+BC+AC
- (d)
\(X=\overline { A } \overline { B } +\overline { B } \overline { C } +\overline { A } \overline { C } \)
Consider the signed binary number A = 01000110 and B =11010011, where B is in 2's complement and MSB is the sign bit. In List I operation is given and in List II resultant binary number is given, match them and find the correct answer using the codes given below the lists.
List I | List II |
---|---|
P. A+B | 1. 1 0 0 0 1 1 0 1 |
Q. A-B | 2. 1 1 1 0 0 1 1 1 |
R. B-A | 3. 0 1 1 1 0 0 1 1 |
S. -A-B | 4. 1 0 0 0 1 1 1 0 |
5. 0 0 0 1 1 0 1 0 | |
6. 0 0 0 1 1 0 1 0 | |
7. 0 1 0 1 1 0 1 1 |
- (a)
P Q R S 5 7 4 2 - (b)
P Q R S 6 3 1 2 - (c)
P Q R S 6 7 1 3 - (d)
P Q R S 5 3 4 2
A PLA realization is shown in figure.
The value of f2(x2 ,x1,x0) is
- (a)
\(\sum { m\left( 1,2,5,6 \right) } \)
- (b)
\(\sum { m\left( 1,2,6,7 \right) } \)
- (c)
\(\sum { m\left( 2,3,4 \right) } \)
- (d)
None of these