Digital System
Exam Duration: 45 Mins Total Questions : 30
A logical expression in the sum of products (SOP) is suitable for implementation using
- (a)
AND gates
- (b)
NOR gates
- (c)
NAND gates
- (d)
EX-OR gates
SOP is suitable for implementation using OR gates or NAND gates.
A certain J-K flip-flop has tnd =12 ns. The largest MOD ripple counter that can be constructed from these flip-flops and still operate upto 10 MHz is
- (a)
8
- (b)
256
- (c)
512
- (d)
10
Let suppose that there is n flip-flops are connected. So, frequency
\(f=\frac { 1 }{ n.{ t }_{ d } } \\ 10\times { 10 }^{ 6 }=\frac { 1 }{ n\times 12\times { 10 }^{ -9 } } \)
n=8
So, \({ 2 }^{ 8 }\)=256 MOD ripple counter can be constructed with the help of it.
Which CMOS circuit shown in figure?
- (a)
positive NAND
- (b)
negative NAND
- (c)
positive NOR
- (d)
negative NOR
V1 | V2 | M1 | M2 | M3 | M4 | V0 |
0 | 0 | off | off | on | on | VDD=V(1) |
0 | VDD | off | on | off | on | 0=V(0) |
VDD | 0 | on | off | on | off | 0=V(0) |
VDD | VDD | on | on | off | off | 0=V(0) |
This represents the function of a positive NOR gate.
An n bit ADC using VR as reference voltage has a resolution (in volt) of
- (a)
\(\frac { { V }_{ R } }{ { 2 }^{ N }-1 } \)
- (b)
\({ V }_{ R }N\)
- (c)
\(\frac { { V }_{ R } }{ { 2 }^{ N-1 } } \)
- (d)
\(2N\times { V }_{ R }\)
For an n-bit ADC its resolution in volt is given by
Resolution =\(\frac { { V }_{ R } }{ { 2 }^{ N }-1 } \)
A 4 bit D/A converter gives an output voltage of 4.5 V for an input code of 1001. The output voltage for an input code of 0110 is
- (a)
1.5 V
- (b)
2.0 V
- (c)
3.0 V
- (d)
4.5 V
Output voltage of a D/A converter
\({ V }_{ 0 }=\frac { { V }_{ R } }{ { 2 }^{ N }-1 } (1+{ 2 }^{ 3 })=\frac { { V }_{ R } }{ 15 } (9)\)
For 1001, \(4.5=\frac { { V }_{ R } }{ 15 } (9)\)
For 0110,
\({ V }_{ 0 }=\frac { { V }_{ R } }{ { 2 }^{ N }-1 } .(2+4)={ V }_{ 0 }=\frac { { V }_{ R } }{ { 2 }^{ N }-1 } .(6)\\ =\frac { { V }_{ R } }{ 15 } (6)\\ =\frac { 4.5 }{ 9 } \times 6\\ =3.0\)
8-bit A/D converter, the quantization error is given by (in per cent)
- (a)
0.392
- (b)
0.521
- (c)
0.212
- (d)
0.425
Quantization error
\(=\frac { 1 }{ { 2 }^{ N }-1 } \times 100\\ =\frac { 10 }{ { 2 }^{ 8 }-1 } \times 100=\frac { 1 }{ 256-1 } \times 100\\ =\frac { 100 }{ 255 } \)
=0.392%
For the DAC shown below step size is 0.5 V. If digital input varies from 0 to 5 V. The value of RF will be
- (a)
800 \(\Omega \)
- (b)
1000 \(\Omega \)
- (c)
750 \(\Omega \)
- (d)
900 \(\Omega \)
Step size=\(\frac { { R }_{ F } }{ 8k } \times 5\)
\(0.5=\frac { { R }_{ F } }{ 8k } \times 5\\ { R }_{ F }=800\Omega \)
A 4 bit modulo-6 ripple counter usesJ-K flip-flop. If the propagation delay of each flip-flop is 70 ns, the maximum clock frequency that can be used is equal to
- (a)
3.1 MHz
- (b)
3.6 MHz
- (c)
4.2 MHz
- (d)
4.9 MHz
Total delay time \({ Nt }_{ d }=4\times 70=280\times { 10 }^{ -9 }\)
\(f=\frac { 1 }{ 280\times { 10 }^{ -9 } } \)
=3.6 MHz
In general block diagram of sequential logic circuit, the clock is given to
- (a)
time delay device
- (b)
output logic
- (c)
memory element
- (d)
Both (a) and (c)
Memory element is provided with clock signal and it is also referred to as time delay device.
If a counter having 10 flip-flops initially at 0, what count will it hold after 2060 pulses?
- (a)
000 000 1110
- (b)
000 001 1100
- (c)
000 001 1000
- (d)
000 000 1100
It completes one cycle= 1024 pulses
For \(\frac { 2048 }{ 1024 } \)= 2 cycles
Balance=2060-2048=12 pulses
Binary 12= 000 000 1100
The output of the circuit shown in below figure is equal to
- (a)
\(AB+\overline { A } \overline { B } \)
- (b)
1
- (c)
zero
- (d)
\(\overline { A } B+A\overline { B } \)
The circuit can be modified as
Inputs to the final Ex-NOR gate are same \(\left( A\bigoplus B \right) \). Hence, output will always be 1.
Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1 bit full adder with input bits P and Q and the carry input Cin. Which of the following combinations of inputs to I0,I1,I2 and I3 of the MUX will realize the sum S?
- (a)
I0=I1=Cin; I2=I3+\(\overline { { C }_{ in } } \)
- (b)
I0=I1=\(\overline { { C }_{ in } } \); I2=I3=Cin
- (c)
I0=I3=Cin; I1=I2=\(\overline { { C }_{ in } } \)
- (d)
I0=I3=\(\overline { { C }_{ in } } \); I1=I2=Cin
For a 4:1 MUX
where, sum of full adder=\(A\bigoplus B\bigoplus C\).
In binary R-2R ladder D/A converter, the input resistance for each inputs is
- (a)
4R
- (b)
R
- (c)
2R
- (d)
None of these
In R-2R ladder D/A converter, the input resistance for each input is 3R.
A n bit A/D converter is required to convert an analog input in the range of 0-15 V to an accuracy of 20 mV. The value of n should be
- (a)
8
- (b)
9
- (c)
10
- (d)
12
Resolution=\(\frac { 15 }{ { 2 }^{ n }-1\quad } \)=20 m
\(\Rightarrow \frac { 15 }{ 20\times { 10 }^{ -3 } } ={ 2 }^{ n }-1\\ \Rightarrow { 2 }^{ n }-1=750\\ \Rightarrow { 2 }^{ n }=751\)
\(\Rightarrow\) n>9
n=10
Match logic family given in List-I with their properties given in List-II and select the correct answer using the codes given below the lists.
List I | List II |
---|---|
TTL | 1. Non-saturation type and high power consumption |
ECL | 2. Low power consumption and high packing density |
CMOS | 3. High switching speed and good fan-out capability |
I2L | 4. Bipolar logic with high packing density |
- (a)
P Q R S 3 1 2 4 - (b)
P Q R S 2 3 1 4 - (c)
P Q R S 4 3 1 2 - (d)
P Q R S 2 4 3 1
TTL- High switching speed and good fan-out capability
ECL-Non-saturation type and high power consumption
CMOS-Low power consumption and high packing density
I2L-Bipolar logic with high packing density
Identify the operation of the circuit in the negative level logic system.
- (a)
AND
- (b)
OR
- (c)
NAND
- (d)
NOR
The truth table for the given function
A | B | Y |
---|---|---|
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
Y=\(\overline { A+B } \)=NOR
Match List I with List II and find the correct answer using the codes given below the lists.
List I | List II |
---|---|
P. A shift register can be used | 1. For code conversion |
Q. A multiplexer can be used | 2. To generate memory clip to select |
R. A decoder can be used | 3. For parallel to serial conversion |
4. As a many to one switch | |
5. For analog to digital conversion |
- (a)
P Q R 1 2 3 - (b)
P Q R 3 4 1 - (c)
P Q R 5 4 2 - (d)
P Q R 1 3 5
Shift register-For parallel to serial conversion
Multiplex-As a many to one switch
Decoder-To generate memory chip select
An 8 bit successive approximation A/D converter has a full-scale reading of 2.55 V and its conversion time for an analog input of 1 V is 20\(\mu s\) . The conversion time for a 2 V input will be
- (a)
10 \(\mu s\)
- (b)
20 \(\mu s\)
- (c)
40 \(\mu s\)
- (d)
50 \(\mu s\)
In successive approximation A/D converter, the conversion time is independent of the analog input voltage. So, conversion time will be 20\(\mu s\)
A sequential circuit using D flip-flop and logic gates is shown below, where X and Y are inputs and Z is the output. Then, the circuit is
- (a)
J-K flip-flop with inputs X=J and Y=K
- (b)
S-R flip-flop with inputs X=R and Y=S
- (c)
S-R flip-flop with inputs X=S and Y=R
- (d)
J-K flip-flop with inputs X=K and Y=J
\(D=\overline { X } { Q }_{ n }+\overline { { Q }_{ n } } Y\)
X | Y | Qn | D | Qn+1 |
---|---|---|---|---|
0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 1 | 1 |
0 | 1 | 0 | 1 | 1 |
0 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 0 |
1 | 0 | 1 | 0 | 0 |
1 | 1 | 0 | 1 | 1 |
1 | 1 | 1 | 0 | 0 |
So, we can see that the circuit works as J-K flip-flop with X=K and Y=J
The circuit realization of the combinational logic block shown in figure to obtain the following table will be
A | B | Q0 |
---|---|---|
0 | 0 | \(\overline { { Q }_{ n } } \) |
0 | 1 | 1 |
1 | 0 | Qn |
1 | 1 | 0 |
- (a)
- (b)
- (c)
- (d)
The state table is as follows:
A | B | J | K | Qn | Qn+1 |
---|---|---|---|---|---|
0 | 0 | 1 | 1 | Qn | Qn |
0 | 1 | 1 | 0 | X | 1 |
1 | 0 | 0 | 0 | Qn | Qn |
1 | 1 | 0 | 1 | X | 0 |
The K-maps for J and K are
The circuit implementation is
The logic function \(f=\overline { \left( x.\overline { y } \right) +\left( \overline { x } .y \right) } \) is the same as
- (a)
\(f=(x+y)(\overline { x } +\overline { y } )\)
- (b)
\(f=\overline { (\overline { x } +\overline { y } )+(x+y) } \)
- (c)
\(f=\overline { (x,y) } .(\overline { x } ,\overline { y } )\)
- (d)
None of the above
Putting x = 1, Y = 1
In given functions and all other options, then check result.
The simplified form of the Boolean expression \(Y=\left( \overline { A } .BC+D \right) \left( \overline { A } D+\overline { B } \overline { C } \right) \) can be written as
- (a)
\(\overline { A } D+\overline { B } \overline { C } D\)
- (b)
\(AD+B\overline { C } D\)
- (c)
\((\overline { A } +D)+(\overline { B } \overline { C } +D)\)
- (d)
\(A\overline { D } +BC\overline { D } \)
\(Y=\left( \overline { A } BC+D \right) \left( \overline { A } D+\overline { B } \overline { C } \right) \\ =\overline { A } BCD+\overline { A } D+\overline { B } \overline { C } D\\ =\overline { A } D(BC+1)+\overline { B } \overline { C } D\\ =\left( \overline { A } D+\overline { B } \overline { C } D \right) \)
In figures, as long as X1 =1 and X 2 =1, the output Q remains
- (a)
at one
- (b)
at zero
- (c)
at its initial value
- (d)
unstable
As no combination of Q with (X1 and X 2) = the output is unstable.
Statement 1 The dynamic memories have lower packing density than static memories.
Statement 2 Dark current is the phenomenon related to static memories.
Of these statements which option is correct?
- (a)
1-True, 2-False
- (b)
1-True; 2-True
- (c)
1-False; 2-True
- (d)
1-False; 2-False
Dynamic memories have higher packing density than static memories. Dark current is the phenomenon related to Charge Coupled Device (CCD). In CCD, the digital input is converted into charge and then, transferred through various stages in a sequential manner. During the charge transfer, a small amount of charge is lost. Also due to thermal effects, undesirable charge may be generated which is known as dark current
For a 8 bit D/A converter used to produce analog signal which controls speed of DC motor rated till 100 rpm speed, the number of steps required to reach speed of 40 rpm is equal to
- (a)
6
- (b)
115
- (c)
102
- (d)
7
Eight bit D/A converter
2n-1=28-1=255 steps
Maximum interval=\(\frac { 100 }{ 255 } \)
These are the steps in which speed can be varied Number of steps required to reach 40 rpm speed
=\(\frac { 40 }{ \left( \frac { 100 }{ 255 } \right) } =\frac { 40\times 255 }{ 100 } =102\)
The CMOS circuit shown in figure, implement
- (a)
\(\overline { AB+CD+E } \)
- (b)
\(\overline { (A+B)(C+D)E } \)
- (c)
AB+CD+E
- (d)
(A+B)(C+D)E
If input signal E is low, the output will not be low. So, it must be high.
For a four bit weighted register D/A converter with logic 1 as 8 V and logic 0 as 0 V, the third LSB will be
- (a)
1/4
- (b)
3/16
- (c)
3/15
- (d)
None of these
Weight assigned to 3rd LSB = \(4\times \frac { 1 }{ { 2 }^{ 4 }-1 } \)
\(=4\times \frac { 1 }{ 15 } =\frac { 4 }{ 15 } \)
Consider the signed binary number A = 01000110 and B =11010011, where B is in 2's complement and MSB is the sign bit. In List I operation is given and in List II resultant binary number is given, match them and find the correct answer using the codes given below the lists.
List I | List II |
---|---|
P. A+B | 1. 1 0 0 0 1 1 0 1 |
Q. A-B | 2. 1 1 1 0 0 1 1 1 |
R. B-A | 3. 0 1 1 1 0 0 1 1 |
S. -A-B | 4. 1 0 0 0 1 1 1 0 |
5. 0 0 0 1 1 0 1 0 | |
6. 0 0 0 1 1 0 1 0 | |
7. 0 1 0 1 1 0 1 1 |
- (a)
P Q R S 5 7 4 2 - (b)
P Q R S 6 3 1 2 - (c)
P Q R S 6 7 1 3 - (d)
P Q R S 5 3 4 2
In 2's complement
A = 01000110
B = 11010011
\(\overline { A } ,\overline { B } \) represents the 2's complement of A and B respectively.
\(\overline { A } \)=01000110
\(\overline { B } \)=11010011
A+B
0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | |
+ | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
A-B
0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | |
+ | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 |
0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
A switching function of four variables, f(w, x, y, z) is equal I to the product of two other functions f1 and f2 , of the same variable f = f1 f2· The functions f and f1 are as follow:
\(f=\sum { m(4,7,15) } \\ f=\sum { m(0,1,2,3,4,7,8,9,10,11,15) } \)
The simplest function for f2 is
- (a)
x
- (b)
\(\overline { x } \)
- (c)
y
- (d)
\(\overline { y } \)
\({ f }_{ 2 }=\sum { m(4,7,15)+\sum { d(5,6,12,13,14) } } \)
A mealy system produces a 1 output if the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1's.
The flip-flop required to !implement this system are
- (a)
2
- (b)
3
- (c)
4
- (d)
5
2n=4
n=2
Thus, two flip-flops are required.