Microprocessor
Exam Duration: 45 Mins Total Questions : 30
What should be the minimum pulse width for the INTR signal is 8085?
- (a)
17.5T-states
- (b)
18 T-states
- (c)
16.5 T-states
- (d)
5.5 T-states
The contents of the Accumulator in an 8085 microprocessor is altered after the execution of the instruction.
- (a)
CMPC
- (b)
CPI 3 A
- (c)
ANI 5C
- (d)
ORA A
Which one of the following is not a vectored interrupt?
- (a)
TRAP
- (b)
INTR
- (c)
RST 3
- (d)
RST 7.5
It desired to multiply the numbers 0AH by 0BH and stored the result in the Accumulator. The numbers are available in registers B and C respectively. A part of the 8085 program for this purpose is given below.
MVI A, 00H
LOOP, ..............
..............
..............
HLT .......
END........
The sequence of instruction to complete the program would be
- (a)
JNZ LOOP, ADD B, DCR C
- (b)
ADD B, JNZ LOOP, DCR C
- (c)
DCR C, JNZ LOOP, ADD B
- (d)
ADD B, DCR C, JNZ LOOP
After the arithmetic operation, the flag register of 8085 \(\mu P\) has the following contents:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
1 | 0 | \(\times \) | 1 | \(\times \) | 0 | \(\times \) | 1 |
The contents of Accumulator after operation may be
- (a)
75
- (b)
6C
- (c)
DB
- (d)
B6
In an 8085 microprocessor, the instruction CMP B has been executed while the contents of accumulator is less than that of register B. As a result carry flag and zero flag will be respectively
- (a)
set, resert
- (b)
reset, set
- (c)
reset, reset
- (d)
set, set
In a microprocessor, the register which holds the address of the next instruction to be fetched is
- (a)
accumulator
- (b)
program counter
- (c)
stack pointer
- (d)
instruction registers
In a microprocessor, WAIT states are used to
- (a)
make the processor WAIT during a DMA operation
- (b)
make the processor WAIT during an interrupt processing
- (c)
make the processor WAIT during a power shunt down
- (d)
interface slow peripherals to the processor
Consider the following 8085 instruction:
XRA A
MVI B, 4AH
SUI 4FH
ANA B
HLT
The contents of registers A and B are respectively
- (a)
05 and 4A
- (b)
4F and 00
- (c)
B1 and 4A
- (d)
None of these
When CPU is interrupted, it
- (a)
stops execution of instructions
- (b)
acknowledge interrupt and branches subroutines
- (c)
acknowledge interrupt and continues
- (d)
acknowledge interrupt and waits for the next instruction from the interrupting device
A DMA transfer implies
- (a)
direct transfer of data between memory and Accumulator
- (b)
direct transfer of data between memory and input devices without use of microprocessor
- (c)
transfer of data exclusively within microprocessor register
- (d)
a fast transfer of data between microprocessor and input device
Consider the following loop:
XRA A
LXI B, 0007H
LOOP: DCX B
JNZ LOOP
This loop will be executed
- (a)
1 time
- (b)
8 times
- (c)
7 times
- (d)
infinite times
An instruction used to set the carry the most computer can be classified as
- (a)
data transfer
- (b)
arithmetic
- (c)
logical
- (d)
memory control
Consider the following program:
MVI A, DATA
MVI B, 64H
MVI C, C8H
CMP B
JC RJCT
CMP C
JNC RJCT
OUT PORT 1
HLT
RJCT: SUB A
OUT PORT 1
HLT
If the following sequence of bytes is located in Accumulator:
DATA (H) | 58 | 64 | 73 | B4 | C8 | FA |
Then, sequence of outputs will be
- (a)
00, 00 73, B4, 00, FA
- (b)
58, 64, 00, 00, C8, FA
- (c)
58, 00, 00, 00, C8, FA
- (d)
00, 64, 73, B4, 00, FA
Consider the following routine:
LXI SP, 2400H
MVI C, 01H
PUSH B
POP PSW
RET
After the execution of this routine, the zero and carry flag will be respectively
- (a)
set, reset
- (b)
set, set
- (c)
reset, set
- (d)
Not affected
The following instructions have been executed by an 8085 μP :
Add (Hex) | Instructions |
---|---|
6010 | LXI H, 8A79 |
6013 | MOV A, L |
6015 | ADD H |
6016 | DAA |
6017 | MOV H, A |
6018 | PCHL |
From which address will the next instruction be fetched?
- (a)
6019
- (b)
6379
- (c)
6979
- (d)
None of these
An 8085 executes the following instructions:
2710 LXI H, 30A0 H
2713 DAD H
2714 PCHL
All addresses and contents are in Hex. Let PC be the contents of the program counter and HL be the contents of HL register pair just after executing PCHL which of the following statement is correct?
- (a)
PC=2715 H, HL=30A0 H
- (b)
PC=30A0 H, HL=2715 H
- (c)
PC=6140 H, HL=6140 H
- (d)
PC=6140 H, HL=2715 H
For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is
3000 MVI A, 45 H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA B
- (a)
00H
- (b)
45 H
- (c)
67 H
- (d)
E7H
In a 8085 microprocessor system memory mapped I/O,
- (a)
I/O devices have 8 bit addresses
- (b)
arithmetic and logic operations can be directly performed with the I/O data
- (c)
there can be maximum of 256 input devices and 256 output devices
- (d)
I/O devices are accessed using IN and OUT instructions
The following sequence of instructions are executed by an 8085 microprocessor
1000 LXI SP, 27 FF
1003 CALL 1006
1006 POP H
The contents of the Stack Pointer (SP) and the HL, register pair on completion of execution of these instruction are
- (a)
SP=27 FD, HL=1003
- (b)
SP=27 FF, HL=1003
- (c)
SP=27 FD, HL=1006
- (d)
SP=27 FF, HL=1006
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. Then, the number of such chips required to design the memory system is
- (a)
16
- (b)
8
- (c)
4
- (d)
2
Match List I with List II and find the correct answer using the codes given below the lists.
List I | List II |
---|---|
P. LDA 2050 H | 1. Direct |
Q. MOV B, A | 2. Indirect |
R. MOV B, M | 3. register |
- (a)
P Q R 1 2 3 - (b)
P Q R 1 3 2 - (c)
P Q R 2 1 3 - (d)
P Q R 2 3 1
If the operating frequency of 8085 is MHz, find the time required to execute MOV A, M.
- (a)
3 \(\mu s\)
- (b)
3.5 \(\mu s\)
- (c)
4 \(\mu s\)
- (d)
4.5 \(\mu s\)
The stack pointer of a microprocessor is at A 001. At the end of execution of following instructions, the value of stack pointer is
PUSH PSW
XTHL
PUSH D
JMP FC 70 H
- (a)
(9FFB)16
- (b)
(9FFC)16
- (c)
(9FFD)16
- (d)
(9FFE)16
An Intel 8085 processor is executing the program given below.
MVI A, 10H
MVI B, 10 H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
The number of times that the operation NOP will be executed is equal to
- (a)
1
- (b)
2
- (c)
3
- (d)
4
The following program is written for an 8085 microprocessor to add two bytes located at memory addresses 1FFE and 1FFF
LXI H, FFE
MOV B, M
INR L
MOV A, M
ADD B
INR L
MOV M, A
XOR A
On completion of the execution of the program, the result ai addition is found
- (a)
in the register A
- (b)
at the memory address 1000
- (c)
at the memory address 1F00
- (d)
at the memory address 2000
In an 8085 microprocessor based system, it is desired to increment the contents of memory location whose address is available in (DE) (register pair and store the result in the same location). The sequence of instruction is
- (a)
XCHG
INRM - (b)
SCHG
INRM - (c)
INX D
XCHG - (d)
INR M
XCHG
In an 8085 microprocessor, the contents of the accumulator, after the following instructions are executed wi II become
XRAA
MVI B F0H
SUB B
- (a)
01 H
- (b)
0F H
- (c)
F0 H
- (d)
10 H
An 8085 assembly language program is given below.
Line No. | Mnemonics | |
---|---|---|
1. | MVI | A, B5H |
2. | MVI | B, OEH |
3. | XRI | 69H |
4. | ADD | B |
5. | ANI | 9BH |
6. | CPI | 9FH |
7. | STA | 3010H |
8 | HLT |
After execution of line 7 of the program, the status of the CY and Z flags will be
- (a)
CY=0, Z=0
- (b)
CY=0, Z=1
- (c)
CY=1,Z=0
- (d)
CY=1,Z=1
Consider the following program of 8085 assembly language:
LXI H 4A02H
LDA 4A00H
MOV B, A
LDA 4A01H
CMP B
JZ FNSH
JC GRT
MOV M, A
JMP FNSH
MOV M, B
FINISH: HLT
The memory requirement for this program is
- (a)
20 H
- (b)
02 H
- (c)
00 H
- (d)
FF H