GATE Electronics and Communication Engineering - Digital Electronics
Exam Duration: 45 Mins Total Questions : 30
Consider the circuit shown in figure:
The expression for the next state Q+ is
- (a)
xQ
- (b)
x\(\oplus \)Q
- (c)
\(x\overset { \_ }{ Q } \)
- (d)
\(x\odot Q\)
The initia contents of the 4 bit serial-in-parallel out shift register, register shown in figure is 0110. After three clock pulses are applied, the content of theshift register will be
- (a)
00000
- (b)
0101
- (c)
1111
- (d)
1010
The counter shown in figure counts from
- (a)
000 to 111
- (b)
111 to 000
- (c)
100 to 000
- (d)
000 to 100
The initial state of MOO-16 down counter is 0110. What will it be after 37 clock pulses?
- (a)
Inddeterminate
- (b)
0101
- (c)
0001
- (d)
0110
Which of the follownig circuit converts a J-K flip-flop to a T flip-flop?
- (a)
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- (b)
-Q.png)
- (c)
-Q.png)
- (d)
-Q.png)
Which of the following logics possesses highest noise immunity?
- (a)
DTL
- (b)
HTL
- (c)
ECL
- (d)
TTL
The gate shown in figure is
- (a)
AND gate
- (b)
NAND gate
- (c)
NOT gate
- (d)
OR gate
The ideal inverter in figure shown has a reference voltage of 2.5 V The forward voltage of the diode is 0.75 V The maximum number of diode logic circuits that may be cascaded ahead of the inverter without producing logic error is
- (a)
3
- (b)
9
- (c)
5
- (d)
4
Consider the CMOS circuit shown in figure. It acts as a
- (a)
negative NAND
- (b)
positive NAND
- (c)
negative NOR
- (d)
positive NOR
An n-bit ADC using \(V_{ R }\) as reference voltage has a resolution (in volt) of
- (a)
\(\frac { V_{ R } }{ 2^{ N }-1 } \)
- (b)
\(V_{ R }N\)
- (c)
\(\frac { V_{ R } }{ 2^{ N-1 } } \)
- (d)
2NX\(V_{ R }\)
11001, 1001 and 111001 correspond to the 2's complement representation of the following set of numbers
- (a)
25, 9 and 57 respectively
- (b)
-6,-6 and -6 respectively
- (c)
-7, -7 and -7 respectively
- (d)
- 25, -9 and -57 respectively
A signed integer has been stored in a byte using 2's complement format. We wish to store the same integer in 16-bit word. We should copy the original byte to the less significant byte of the word and fill the more significant byte with
- (a)
0
- (b)
1
- (c)
equal to the MSB of the original byte
- (d)
complement of the MSB of the original byte
Identify the operation of circuit in negative level logic system
- (a)
AND
- (b)
OR
- (c)
NAND
- (d)
NOR
The circuit shown in figure is a 4-bit DAC. The input bits 0 and 1 are represented by 0 and 5 V respectively. The op-amp is ideal but all the resistances and the 5 V inputs have tolerance of ±1O%. The simplification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is
- (a)
±35&
- (b)
±20%
- (c)
±10%
- (d)
±5%
The circuit given below is
- (a)
J-K flip flop
- (b)
Johnson's counter
- (c)
RS latch
- (d)
None of these
Wired logic is not possible in
- (a)
ECL
- (b)
TTL with active pull-up
- (c)
open-collector TTL
- (d)
TTL with passive pull-up
The counter shown in figure is a
- (a)
MOD-8 up counter
- (b)
MOD-8 down counter
- (c)
MOD-6 up counter
- (d)
MOD-6 down counter
A MUX network is shown in figure .
Z2=?
- (a)
ab+bc+ca
- (b)
a+b+c
- (c)
abc
- (d)
\(a\odot b\odot c\)
The building block shown in figure is an active high output decoder
The output X is
- (a)
AB+BC+CA
- (b)
A+B+C
- (c)
ABC
- (d)
None of these
The circuit shown in figure implements the function
- (a)
\(ABC+\overline { ABC } \)
- (b)
\(ABC+\overline { (A+B+C) } \)
- (c)
\(\overline { ABC } +\overline { (A+B+C) } \)
- (d)
None of these
The divide by N counter is shown in figure If initially Q0=1,Q1 =1,Q2 =0. what is a value of N?
- (a)
8
- (b)
6
- (c)
5
- (d)
3
A PLA realization is shown in figure
\({ f }_{ 1 }\left( { x }_{ 2 },{ x }_{ 1 },{ x }_{ 0 } \right) =?\)
- (a)
\({ x }_{ 2 }\overline { { x }_{ 0 } } +{ x }_{ 1 }{ x }_{ 0 }\)
- (b)
\({ x }_{ 2 }{ x }_{ 0 }+{ x }_{ 1 }\overline { { x }_{ 2 } } \)
- (c)
\({ x }_{ 2 }\oplus { x }_{ 0 }\)
- (d)
\({ x }_{ 2 }\odot { x }_{ 0 }\)
A PLA realization is shown in figure .
f3(x2,x1,x0)=?
- (a)
\(\Pi M(0,4,6,7)\)
- (b)
\(\Pi M(2,4,5,7)\)
- (c)
\(\Pi M(1,2,3,5)\)
- (d)
\(\Pi M(2,3,4,7)\)
Consider the RTL circuit of figure:
If V01 is taken as the output, then circuit is a
- (a)
AND
- (b)
OR
- (c)
NAND
- (d)
NOR
Consider the circuit of figure:
If V02 is taken as the output, the logic is
- (a)
AND
- (b)
OR
- (c)
NAND
- (d)
NOR
A mealy system produces a 1 output if the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1's.
The flip-flop required to implement this system are
- (a)
2
- (b)
3
- (c)
4
- (d)
5
The output of the 4x1 multiplexer shown below is
- (a)
X+Y
- (b)
\(\overline { X } +Y\)
- (c)
\(X\overline { Y } +X\)
- (d)
XY
The initial contents of 4-bit serial in-parallel out right shift register shown below is 0110 After three clock pulses are applied the contents of shift register will be
- (a)
0000
- (b)
0101
- (c)
1010
- (d)
1111
A 10-bit D/A converter provides an analog output which has a maximum value of 10.23 V, The resolution is
- (a)
10 mV
- (b)
20 mV
- (c)
15 mV
- (d)
25 mV
In the digital to analog converter circuit shown in the figure below, VR =10 V and R=10 \(\Omega \).
The voltage V0 is
- (a)
-0.781 V
- (b)
-1.562V
- (c)
-3.125 V
- (d)
-6.250 V
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