GATE Electronics and Communication Engineering - Microprocessors
Exam Duration: 45 Mins Total Questions : 30
Consider the sequence of 8085 instruction given
below
LXI H, 9258 MOV A, M CMA MOV M, A
Which one of the following is performed by this sequence?
- (a)
Contents of location 9258 are moved to the accumulator
- (b)
Contents of location 9258 are compared with the contents of the accumulator
- (c)
Contents of location 8529 are complemented and stored in location 8529
- (d)
Contents of location 5892 are complemented and stored in location 5892
Step 1 :H=92andL=58
Step 2 : A = Content at memory add 9258
Step 3: \(A\leftarrow \overline { A } \)
Step 4 : Content of A will store at memory location 9258.
It is desired to multiply the numbers 0AH by OBH and store the result in the accumulator. The numbers are available in registers Band C respectively. A part of the 8085 program for this purpose is given below.
MVI A, 00H
LOOP, ..................
..................
..................
HLT............
END...........
The sequence of instruction to complete the program would be
- (a)
JNZ LOOP, ADD B, OCR C
- (b)
ADD B, JNZ LOOP, OCR C
- (c)
OCR C, JNZ LOOP, ADD B
- (d)
ADD B, OCR C, JNZ LOOP
To perform the multiplication of OA and OB stored at Band C, the program requires addition of content of B to accumulator to C times.
MVI A, 00H ⇢lear accumulator
LOOP: ADD B ⇢ [B) + [A] ~ [A]
DCR C ⇢ Decrement C
JNZ, LOOP ⇢ If C is not zero, jump to Loop
HLT
END
After an arithmetic operation, the flag register of 8085 uP has the following contents:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
1 | 0 | X | 1 | X | 0 | X | 1 |
The contents of accumulator after operation may be
- (a)
75
- (b)
6C
- (c)
DB
- (d)
B6
The bit positions in flag register are as follows
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
S | Z | X | AC | X | P | X | CY |
S= 1, P=O
Result must have odd parity and D7 = 1.
Following is the statement of a 8085 assembly language program
LXI SP, EFFFH
CALL 3000 H
:
:
:
3000 H : LXI H, 3CF4 H
PUSH PSW
SPHL
POP PSW
RET
On completion of RETexecution, the content of SP is
- (a)
3CF0 H
- (b)
3CFB H
- (c)
3FFD H
- (d)
EFFFH
LXI SP, EFFF H ; Load SP with data EFFH
CALL 3000 H; Jump to location 3000H
:
:
3000H LXIH, 3CF4 ; Load HL with data 3CF4H
PUSH PSW ; Store contents of PSW to stack
SPHL ; Copy contents of HL to SP (3CF4H)
POP PSW ; Restore contents of PSW
RET ; Stop
Before instruction SPHL the content of SP is 3CF4H.
After execution of POP PSW, SP + 2 ⇢ SP
After execution ofRET, SP + 2 ⇢ SP
Thus, the contents of SP will be 3CF4H + 4 = 3CF8H.
In a microprocessor, WAIT states are used to
- (a)
make the processor WAIT during a DMA operation
- (b)
make the processor WAIT during an interrupt processing
- (c)
make the processor WAIT during a power shunt down
- (d)
interface slow peripherals to the processor
To make the processor Wait during a DMA operation.
It is desired to mask is the high order bits (07 - 04) of the data bytes in register C. Consider the following set of instruction:
(P) MOV A, C
ANI FOH
MOV C, A
HLT
(Q) MOV A,C
MVI B, FOH
ANA B
MOV C,A
HLT
(R) MOV A,C
MVI B, 0FH
ANA B
MOV C,A
HLT
(S) MOV A,C
ANI 0FH
MOV C, A
HLT
The instruction set (S), which execute(s) the desired operation is/are
- (a)
P and Q
- (b)
Rand S
- (c)
only P
- (d)
only S
Instruction set P and Q mask the lower order bits, not high order bits
ANI 0FH ; A AND 0FH➝A
ANA B ; A AND B➝A
Consider the following 8085 instruction
XRA A
MVI B,4AH
SUI 4FH
ANA B
HLT
The contents of registers A and B are, respectively
- (a)
O5,4A
- (b)
4F, 00
- (c)
B1, 4A
- (d)
None of these
XRA A ; Clear A
MVl B, 4AH ; 4A⇢B
SUI 4FH ; A-4FH⇢A=B1H
ANA B
HLT
A = 00, B =4A
When a CPU is interrupted, it
- (a)
stops execution of instructions
- (b)
acknowledge interrupt and branches subroutines
- (c)
acknowledge interrupt and continues
- (d)
acknowledge interrupt and waits for the next instruction from the interrupting device
When an interrupt is acknowledged, CPU performs following
steps:
(i) CPU saves the PC contents on the stack.
(ii) it jumps to a vector location according to interrupt
Consider the following 8085 assembly program:
MVI B,89H
MOV A, B
MOV C, A
MVI D,37H
OUT PORT1
HLT
The output at PORT1 is
- (a)
89
- (b)
37
- (c)
00
- (d)
None of these
MVI B, 89H ; 89 ⇢ B
MOV A,B ;B⇢A
MOV C, A ;A⇢C
MVI D, 37 H ; 37 ⇢ D
OUT PORT1 ; Display A
The content of A is 89H.
Consider the sequence of 8085 instruction
MVI A,5EH
AOI A2H
MOV C, A
HLT
The initial contents of register and flag are as follows
A | C | S | Z | Y |
xx | xx | 0 | 0 | 0 |
After execution of the instructions, the contents of register and flags are
- (a)
A C S Z CY 10H 10H 0 0 1 - (b)
A C S Z CY 10H 10H 1 0 0 - (c)
A C S Z CY 00H 00H 1 1 0 - (d)
A C S Z CY 00H 00H 0 1 1
A | C | S | Z | CY | ||
xx | xx | 0 | 0 | 0 | ||
MVI | A, 5EH | 5E | xx | NA | NA | NA |
ADI | A2H | 00 | xx | 0 | 1 | 1 |
MOV | C, A | 00 | 00 | NA | NA | NA |
HLT |
The total number of memory accesses involved (including of the op-code fetch) when an 8085 microprocessor executes the instruction LDA 2003 is
- (a)
1
- (b)
2
- (c)
3
- (d)
4
LDA 2000
I 3 and 2
1 : Fetch of Op-code
2 and 3: Fetch of 8-bit number once a time, data at add. So, total number of fetch (memory access) = 4 times.
The instruction, that does not clear the accumulator of 8085, is
- (a)
XRA A
- (b)
ANI 00H
- (c)
MVI A, 00H
- (d)
None of these
All instructions clear the accumulator.
XRA A ; A\(\oplus \) A
ANI 00H : A AND 00
MVI A ; 00⇢A
Consider the following loop:
XRA A
LXI B,0007H
LOOP: DCX B
JNZ LOOP
This loop will be executed
- (a)
1 times
- (b)
8 times
- (c)
7 times
- (d)
infinite times
The instruction XRA will set the Z flag. LXI and DCX do not alter the flag. Hence, this loop will be executed I times.
Consider the following loop:
LXI H, 000AH
LOOP: DCX B
MOV A, B
ORA C
JNZ LOOP
This loop will be executed
- (a)
1 time
- (b)
10 time
- (c)
11 times
- (d)
infinite times
LXI B, 000AH ; 00⇢C, 0AH⇢B
LOOP: DCX B ; CB-1⇢B Flat not affected
MOV A, B ; B⇢A
ORA C ; A OR C⇢A, set flag
JNZ LOOP
Hence, this loop will be executed at OAH or ten times.
The contents of accumulator after the execution of following instruction will be
MVI A, A7H
OR A A
RLC
- (a)
CFH
- (b)
4FH
- (c)
4EH
- (d)
CEH
MVI A, B7H ; B7H-+ A
ORA A ; Set Flags, CY = I
RLC ; Rotate accumulator left
The contents of bit D7 are placed in bit Do.
Accumulator
Before RLC 10100111
After RLC 010011 I I
An instruction used to set the carry the most computer can be classified as
- (a)
data transfer
- (b)
arithmetic
- (c)
logical
- (d)
memory control
Arithmetic and logical instructions are used to set the carry
Consider the following set of instruction:
MVI A, BYTE1
RLC
MOV B, A
RLC
RLC
ADD B
If BYTE1 = 07H, then content of A after the execution of program wi II be
- (a)
46H
- (b)
70H
- (c)
38H
- (d)
68H
This program multiplies BYTEI by 10. Hence, content of A will be 46H.
07H = 0710 7 x 10 = 70, 7010 = 46H
Consider the following instruction to be executed by an 80851lP. The input port has an address of 01 H and has a data 05H to input
IN 01H
ANI 80H
After execution of the two instructions, the contents of flag register are
- (a)
1 0 x 1 x 1 x 0
- (b)
0 1 x 0 x 1 x 0
- (c)
0 1 x 1 x 1 x 0
- (d)
0 1 x 1 x 0 x 0
05H ADD 80 H = 00
After the ANI instruction S, Z and P are modified to reflect the result of operation. CY is reset and AC is set. Thus, S=0,Z=1,AC=1, P=1,CY=0
Consider the execution of the following instruction by 8085 \(\mu P\)
MVI H, 01 FFH
SHLD 2050H
After execution the contents of memory, locations 2050H, 2051 H and registers H, L wi II be respectively
- (a)
01 H, FFH, FFH, 01 H
- (b)
FFH, 01 H, FEH, 01 H
- (c)
FFH, 01 H, 01 H, FFH
- (d)
01 H, FFH, 01 H, FFH
Instructions load the register pair HL with 01FFH. SHLD instructions store the contents of L in the memory location 2050H and content of H in the memory location 2051 H. Contents of HL are not altered.
Consider the following routine:
LXI SP, 2400H
MVI C,01H
PUSH B
POP PSW
RET
After the execution of this routine, the zero and carry flag will be respectively
- (a)
set, reset
- (b)
set, set
- (c)
reset, set
- (d)
Not affected
The instruction PUSH B stores the contents of BC at stack. The POP PSW instruction copies the contents of BC into PSW. The contents of register C will be copied into flag register.
D0 = 1 = Carry flag, D6 = 0 = Zero flag.
Hence, zero flag will be reset and carry will be set.
Consider the following set of 8085 instruction:
MVI A, DATAl
ORA A
JP DSPLY
XRA A
DSPLY : OUT PORT1
HLT
If DATA1 = 92H, the output at PORT1 is
- (a)
00
- (b)
FFH
- (c)
92H
- (d)
None of these
MVI A DATAl ; DATA1➝ A
ORA A ; Set flag
JP DSPLY ; If A is.positive, then jump to DSPL Y
XRA A Clear A
DSPLY OUT PORT!; A-.; PORT2
HLT
If DATA1 is positive, it will be displayed at port 1 otherwise 00.
The following instructions have been executed by an 8085 μP
Add (Hex) | Instructions |
---|---|
6010 | LX1 H,8A79 |
6013 | MOV A, L |
6015 | ADD H |
6016 | DAA |
6017 | MOV H, A |
6018 | PCHL |
From which address will the next instruction be fetched?
- (a)
6019
- (b)
6379
- (c)
6979
- (d)
None of these
Step 1 : H = 8A and L = 79
Step 2: A = 79
Step 3 : A = 79 + 8A = 03
Step 4 : In this step, 8-bit number in ACC to form BCD number assuming that earlier operation was BCD addition.
So, in Step3, upper nibble addition generates carry. Therefore, according to BCD addition in upper nibble, 0110 will be added and A = 63H,
Step 5: H = 63
Step 6: PC = 6379
So, next instruction will be fetch from 6379.4.
An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped, I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its three ports and the control register. The address lines A3 to A7 as well as the 10/M signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is
- (a)
F8H-FBH
- (b)
F8H-FCH
- (c)
F8H-FFH
- (d)
F0H-F7H
Chip 8255 will be selected if bits A3 to A7 are 1. Bit A0 to A2 can be 0 or 1. Thus, address range is
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | F8H |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | FFH |
An I/O peripheral device shown in figure below is to be interfaced to an 8085 microprocessor. To select the I/O device in the I/O address range D4H-D7 H, its Chip Select \((\overline { CS } )\) should be connected to the output of the decoder shown in as ahead
- (a)
output 7
- (b)
output 5
- (c)
output 2
- (d)
output 0
The output is taken from the 5th line.
If \((\overline { CS } )=\overline { A_{ 15 } } \)= A14 A13 is used as Chip Select logic of a 4 k RAM in an 8085 system. Then its memory range will be
- (a)
3000 H - 3FFFH
- (b)
7000 H - 7FFFH
- (c)
5000 H - 5FFFH and 6000 H - 6FFFH
- (d)
6000 H - 6FFFH and 7000 H - 7FFFH
4 k = 22, add line = 12, for chip selection \(\overline { A_{ 15 } } \) A14 A13 = 1.For that A15 = 0, A14 = I and A13 = 1.
A15 | A14 | A13 | A12 | A11 | A10 | A9 | A8 |
0 | 1 | 1 | x | 0 | 0 | 0 | 0 |
0 | 1 | 1 | x | 1 | 1 | 1 | 1 |
A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
If A12 = 0, then range is 6000 to 6FFF and if A12 = I, then range is 7000 to 7FFF.
For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is
3000 MVI A, 45 H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA
- (a)
00 H
- (b)
45 H
- (c)
67 H
- (d)
E7H
Content of Register
MVl A, 45 ➝ A = 45
MOV B,A ➝ B=45
STC ➝ CY= 1
CMC ➝ CY=0
RAR ➝ A=22
XRAB ➝ A = 22\(\oplus \)45
A=67H
Consider the following 8085 μP assembly program:
Line No. | Mnemonics | |
---|---|---|
1. | LXI | Sp,0400 H |
2. | LXI | B, 2055 H |
3. | LXI | H, 22FFH |
4. | LXI | D,2090H |
5. | PUSH | H |
6. | PUSH | B |
7. | MOV | A, L |
............ | ||
............ | ||
............ | ||
............ | ||
20. | POP | H |
When line 5 is executed, the contents of memory location 03FEH will be
- (a)
FFH
- (b)
22H
- (c)
20H
- (d)
90H
Line 5 pushes the content of HL register pair on stack. The contents of L will go to 03FFH and contents of H will go to 03FEH. Hence, memory location 03FEH contains 22H.
Consider the following 8085 μP assembly program:
Line No. | Mnemonics | |
---|---|---|
1. | LXI | Sp,0400 H |
2. | LXI | B, 2055 H |
3. | LXI | H, 22FFH |
4. | LXI | D,2090H |
5. | PUSH | H |
6. | PUSH | B |
7. | MOV | A, L |
............ | ||
............ | ||
............ | ||
............ | ||
20. | POP | H |
After the execution of line 20, the contents of register pair HL will be
- (a)
2090H
- (b)
5520H
- (c)
2055H
- (d)
9020H
Contents of register pair B lie on the top of stack when POP H is executed, HL pair will be loaded with the contents of register pair B.
An 8085 assembly language program is given below.
Line No. | Mnemonics | |
---|---|---|
1. | MVI | A, B5H |
2. | MVI | B, OEH |
3. | XRI | 69H |
4. | ADD | B |
5. | ANI | 9BH |
6. | CPI | 9FH |
7. | STA | 3010H |
8. | HLT |
The contents of the accumulator just after execution of the ADD instruction in line 4 will be
- (a)
C3H
- (b)
EAH
- (c)
DCH
- (d)
69H
Line 1 : MVI A, B5H ; Move B5H to A
2: MVI B ; Move OEH to B
3: XRI 69H ; [A] XOR 69H and store in A, content of A is CDH
4: ADD B ; Add the contents of A to contents of B and store
5: ANI 9BH ; [A] AND 9BH, and store in A, content of A is 8AH
6: CPI 9FH ; Compare 9FH with the contents of A Since, 8AH < 9BH, CY = 1
7: STA 3010H ; Store the contents of A to location 30 10 H
8: HLT ; Stop
Thus, the content of accumulator after execution of ADD instruction is EAH
Consider the following program of 8085 assembly language:
LXI H 4A02H
LDA 4A00H
MOV B, A
LDA 4A01H
CMP B
JZ FNSH
JC GRT
MOV M, A
JMP FNSH
MOV M, B
FNSH: HLT
The memory requirement for this program is
- (a)
20 byte
- (b)
21 byte
- (c)
23 byte
- (d)
18 byte
Operand R, M or implied: l-Byte instruction
Operand 8-bit : 2-byte instruction
Operand 16-bit : 3-byte instruction
3-byte instructions are: LXI, LDA, JZ, JC, JMP
P-byte instructions are : MOV, CMP HL T
Hence, memory = 3 x 6 + 1 x 5 = 23-bytes