Computer Science and Information Technology - Computer Organization and Architecture
Exam Duration: 45 Mins Total Questions : 30
Which of the following statements is correct about Booth's algorithm in general form .......
- (a)
In general in the booth scheme-1 times shifted multiplicated is selected when moving from 0 to 1
- (b)
In general in the booth scheme-1 times shifted multiplicated is selected when moving from 1 to 0
- (c)
Neither (a) nor (b)
- (d)
Both (a) and (b)
The booth algorithm
(1) generates a 2n-bit product.
(2) treats both positive and negative 2's complements n-bit operand uniformly.
- (a)
1
- (b)
1, 2
- (c)
2
- (d)
Neither (1) nor (2)
Addresssing mode facilities access to an operand whose location is defined in relative to the beginning of the data structure in which it appears
- (a)
absolute
- (b)
immediate
- (c)
index
- (d)
indirect
Which of the following instructions requires 1-address space?
- (a)
2050
- (b)
LDA 2010
- (c)
MOV 05
- (d)
1 NRA
The number of references required for CPU to execute direc mode address reference is
- (a)
0
- (b)
1
- (c)
2
- (d)
3
Match the following in context of an 8085 uP.
| A. DAA | 1. Program control instruction |
| B. LXI | 2. Data movement instruction |
| C. RST | 3. Interrupt instruction |
| D. JMP | 4. instruction |
- (a)
A B C D 1 2 3 4 - (b)
A B C D 4 2 3 1 - (c)
A B C D 3 2 1 4 - (d)
A B C D 2 3 4 1
Linkage between CPU and the user is procided by
- (a)
peripheral devices
- (b)
control unit
- (c)
storage
- (d)
software
A microprogrammed control unit
- (a)
as faster than a hard wired control unit
- (b)
facilities easy implementation of new instruction
- (c)
is useful when very small program are to be use
- (d)
usually refers to the control unit of a microprocessor
Interrupt driven I/O
- (a)
has its main drawback in the software overhead of interrupts
- (b)
may be better than busy waiting I/O since, less hardware support is required.
- (c)
is equal or faster than DMA for a signal word register
- (d)
Both (a) and (c)
Which of the following is correct?
- (a)
Paging system is invented to get a large linear address space without having to by more physical memory
- (b)
Segmentation is invented to allow programs and data to be broken up into logicality independent address space and to add sharing and protection.
- (c)
Both (a) and (b)
- (d)
Neither (a) nor (b)
The ability to temporarily halt the CPU and use this time to send information on basis is called
- (a)
direct memory access
- (b)
vectoring the interrupt
- (c)
palling
- (d)
cycle stealing
A pipeline is having speed up factor as 10 and operating with effiency of 80%. What will be the number of stages in the pipeline?
- (a)
10
- (b)
8
- (c)
13
- (d)
None of these
A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is
- (a)
256 x 16
- (b)
4k x 6
- (c)
64k x 8
- (d)
64 k x 16
Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and word fields are respectively.
- (a)
7, 7, 6
- (b)
9, 6, 5
- (c)
7, 5m 8
- (d)
9, 5, 8
Daisy chain is for
- (a)
connecting number of devices to controller
- (b)
connecting number of controllers to a device
- (c)
interconnecting number of devices to number of controllers
- (d)
None of the above
A stack is a set of
- (a)
reserved ROM space
- (b)
reserved RAM address space
- (c)
reserved I/O address space
- (d)
None of the above
Risk processors are characterized by
1. variable length instruction formats.
2. prefetch execution.
3. delayed loads and branches
4. data transfer instructions are limited to load and store
- (a)
1, 2, 3
- (b)
1, 2, 4
- (c)
1, 3
- (d)
2, 3, 4
DRAM stores information using
- (a)
capacitors
- (b)
transistors
- (c)
register
- (d)
None of these
The number of memory references required by CPU to execute immediate addressing mode is
- (a)
0
- (b)
1
- (c)
2
- (d)
3
Technique used by CPU to identify a device
- (a)
software pall
- (b)
daisy chain
- (c)
Both (a) and (b)
- (d)
None of these
Which of the following statements is correct about the program counter?
I. Program counter points to the instruction to be executed .
II.The program counter contents are used as address and instruction is read from memory.
- (a)
I only
- (b)
II only
- (c)
I and II
- (d)
Neither I nor II
The following diagram shows which addressing mode?
- (a)
Immediate addressing mode
- (b)
Direct addressing mode
- (c)
Extended addressing mode
- (d)
Register addressing mode
Addressing mode are
- (a)
Explicity specified
- (b)
Implied by the instruction
- (c)
Both (a) and (b)
- (d)
Neither (a) nor (b)
Which of the following is the internal memroy of system?
- (a)
CPU register
- (b)
Cache
- (c)
Main memory
- (d)
All of these
Find the average access time experienced by the CPU in a system with two levels of cahe if
h1 = the hit rate in the primary cache.
c1 = the time to access information in the primary cache.
c2 = the time to access information in the secondary cache
M = the time to access information in the main memory
- (a)
h1c2 + h2c2 + (1-h1h2) M
- (b)
h1c1 - h2c2+(1-h1h2) M
- (c)
h1c1 + (1-h2)h1c2 + (1-h1)(1-h2) M
- (d)
h1c1 + (1-h1)h2c2 + (1-h1)(1-h2) M
Which of the following may not occur in an instruction cycle
1. Fetch
2. Excute
3. Indirect
- (a)
1 only
- (b)
2 only
- (c)
3 only
- (d)
None of these
What is the hit ratio of cache, if a system performs memory access at 300 ns with the cache and 150 ns without it? Assume that the average access time of memory is 42 ns.
- (a)
81%
- (b)
75%
- (c)
92%
- (d)
87%
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number?
- (a)
17, 21
- (b)
21, 17
- (c)
6, 10
- (d)
None of these
Assuming that a cache of 2k blocks (1 block size = 4 word = 16 byte) and 32-bit address. Assume this machine is byte addressable.
What is the bit length of each field in 2-way set associative?
- (a)
19, 11, 2
- (b)
20, 11, 2
- (c)
21, 9, 2
- (d)
None of these
An address space is specified by 24-bit and the correspondence memory space is 16 bit.
How many wrds are there in address space?
- (a)
1 M Words
- (b)
64 k Words
- (c)
16 k Words
- (d)
64 m Words
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