Electrical Engineering - Microprocessor
Exam Duration: 45 Mins Total Questions : 30
What should be the minimum pulse width for the INTR signal is 8085?
- (a)
17.5T-states
- (b)
18 T-states
- (c)
16.5 T-states
- (d)
5.5 T-states
Which one of the following is not a vectored interrupt?
- (a)
TRAP
- (b)
INTR
- (c)
RST 7.5
- (d)
RST3
In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that register B. As a result
- (a)
carry flag will be but zero flag will be reset
- (b)
carry flag will be reset but zero flag will be set
- (c)
both carry flag and zero flag will be reset
- (d)
both carry flag and zero flag will be set
It desired to multiply the numbers 0AH by 0BH and stored the result in the Accumulator. The numbers are available in registers B and C respectively. A part of the 8085 program for this purpose is given below.
MVI A, 00H
LOOP, ..............
..............
..............
HLT .......
END........
The sequence of instruction to complete the program would be
- (a)
JNZ LOOP, ADD B, DCR C
- (b)
ADD B, JNZ LOOP, DCR C
- (c)
DCR C, JNZ LOOP, ADD B
- (d)
ADD B, DCR C, JNZ LOOP
In an 8085 microprocessor, the instruction CMP B has been executed while the contents of accumulator is less than that of register B. As a result carry flag and zero flag will be respectively
- (a)
set, resert
- (b)
reset, set
- (c)
reset, reset
- (d)
set, set
It is desired to mask in the high order bits (D7-D4) of the data bytes in register C. Consider the following set of instruction:
(A) MOV A, C
ANI F0H
MOV C, A
HLT
(B) MOV A,C
MVI B, F0H
ANA B
MOV C, A
HLT
(C) MOV A,C
MVI B, 0FH
ANA B
MOV C, A
HLT
The instruction set(s), which execute(s) the desired operation is/are
(D) MOV A, C
ANI 0FH
MOV C, A
HLT
- (a)
A and B
- (b)
C and B
- (c)
only A
- (d)
only D
Consider the following 8085 instruction:
XRA A
MVI B, 4AH
SUI 4FH
ANA B
HLT
The contents of registers A and B are respectively
- (a)
05 and 4A
- (b)
4F and 00
- (c)
B1 and 4A
- (d)
None of these
Match List I with List II while data moving between registers of the 8085 and the stack and select the correct answer using the codes given below the lists.
List I | List II |
---|---|
P. A PUSH instruction | 1. Pre-increment the stack |
Q. A POP instruction | 2. Post-increments the stack |
3. Pre-decrement of stack pointer | |
4. Post-decrement of stack pointer |
- (a)
P Q 1 4 - (b)
P Q 4 2 - (c)
P Q 3 2 - (d)
P Q 2 4
An input processor controls line flow of information between
- (a)
cache memory and input device
- (b)
main memory and input device
- (c)
two input devices
- (d)
cache and memories
Consider the following set of instruction:
MVI A, BYTE 1
RLC
MOV B, A
RLC
RLC
ADD B
If BYTE 1=07H, then content of A after the execution of program will be
- (a)
46H
- (b)
70H
- (c)
38H
- (d)
68H
Consider the following program:
MVI A, BYTE1
RRC
RRC
If BYTE1=32H the contents of A after the execution of program will be
- (a)
08H
- (b)
8CH
- (c)
12H
- (d)
None of these
Consider the following instruction to be executed by an 8085 \(\mu P\) . The input port has an address of 01H and has a data 05H to input|
IN 01H
ANI 80H
After execution of the two instructions, the contents of flag register are
- (a)
\(1\ \left| 0 \right| \times \left| 1 \right| \times \left| 1 \right| \times \left| 0 \right| \)
- (b)
\(0\ \left| 1 \right| \times \left| 0 \right| \times \left| 1 \right| \times \left| 0 \right| \)
- (c)
\(0\ \left| 1 \right| \times \left| 1 \right| \times \left| 1 \right| \times \left| 0 \right| \)
- (d)
\(0\ \left| 1 \right| \times \left| 1\right|\times \left| 0\right| \times \left| 0 \right| \)
An 8085 μP based system drives a multiplexed 5-digit 7-segment display. The digits are refreshed at a rate of 500 Hz. The ON time for each digit is
- (a)
4 ms
- (b)
0.4 ms
- (c)
10 ms
- (d)
25 ms
The following program is run on 8085 microprocessor:
Memory add in Hex | Instruction | |
---|---|---|
1 | 2000 | LXI SP, 1000 |
2. | 2003 | PUSH H |
3. | 2004 | PUSH D |
4. | 2005 | CALL, 2050 |
5. | 2008 | POP H |
6. | 2009 | HLT |
At the completion of step 4 execution of program the PC of 8085 contains and SP contains will be respectively
- (a)
2050 H, 0FFAH
- (b)
2008 H, 0FFFH
- (c)
2009 H, 1000H
- (d)
2009H, 0FFCH
The following sequence of instructions are executed by 8085 microprocessor:
1000 LX1 SP 27FF
1003 CALL 1006
1006 POP H
The content of the SP and HL register pair on completion of execution of these instructions are
- (a)
SP=27FF, HL=1003
- (b)
SP=27FD, HL=1003
- (c)
SP=27FF, HL=1006
- (d)
SP=27FD, HL=1006
Consider the following routine:
LXI SP, 2400H
MVI C, 01H
PUSH B
POP PSW
RET
After the execution of this routine, the zero and carry flag will be respectively
- (a)
set, reset
- (b)
set, set
- (c)
reset, set
- (d)
Not affected
An 8085 executes the following instructions:
2710 LXIH, 30AOH
2713 DAD H
2714 PCHL
All addresses and constants are in Hex. Let PC be the contents of the program counter and HL be the contents of the HL register pair just after executing PCHL. Which of the following statements is correct?
- (a)
PC = 2715H
HL = 30AOH - (b)
PC = 30AOH
HL = 2715H - (c)
PC = 6140H
HL = 6140H - (d)
PC = 6140H
HL = 2715H
The decoding circuit shown in figure ahead has been used to generate the active low chip select signal for a microprocessor peripheral (the address lines are designated as A0 to A7 for input addresses). The peripheral will correspond to input address in the range
- (a)
60H to 63H
- (b)
A4 H to A7H
- (c)
30H to 33H
- (d)
70H to 73H
If \(\overline { CS } \) = \(\overline { A_{ 15 } } \) A14 A13 is used as chip select logic of a 4 k RAM in an 8085 system. Then its memory range will be
- (a)
3000 H - 3FFF H
- (b)
7000 H - 7FFF H
- (c)
5000 H - 5FFFH and 6000 H - 6FFF H
- (d)
6000 H - 6FFFH and 7000 H - 7FFF H
A computer system has a 4k word cache organized in blockset associative manner with 4 blocks per set, 64 words per block. The number of bits in the SET and WORD fields of the main memory address formula is
- (a)
4, 6
- (b)
6, 4
- (c)
7, 2
- (d)
15, 4
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. Then, the number of such chips required to design the memory system is
- (a)
16
- (b)
8
- (c)
4
- (d)
2
It is necessary to multiply numbers 0A H by 0B H and store the result in A. The numbers are available in registers B and C respectively. A part of 8085 program for this purpose is given.
MVI A, 00H
LOOP: ..........
...........
..........
HLT
END
The sequence of instructions to complete the program would be
- (a)
JNZ LOOP
ADD B - (b)
ADDB
DCR C - (c)
DCR C
JNZ LOOP
ADD B - (d)
ADD B
JNZ LOOP
DCR C
The contents of memory locations 2017 H and 210D H after execution of the following instruction.
LXI H H, 2107 H
MVI B09 H
MVI A, 01
LOOP: MOOV M, A
INR A
INX H
DCR B
JNZ LOOP
HLT
- (a)
00, 07
- (b)
01, 08
- (c)
01, 09
- (d)
01, 07
The number of times the loop will be executed is
LXI B, 0007 H
LOOP DCX B
MOOV A, B
ORA C
JZ LOOP
- (a)
6
- (b)
2
- (c)
7
- (d)
1
The number of T-states to execute CALL instruction is
- (a)
21
- (b)
13
- (c)
18
- (d)
16
The following program is written for an 8085 microprocessor to add two bytes located at memory addresses 1FFE and 1FFF
LXI H, FFE
MOV B, M
INR L
MOV A, M
ADD B
INR L
MOV M, A
XOR A
On completion of the execution of the program, the result ai addition is found
- (a)
in the register A
- (b)
at the memory address 1000
- (c)
at the memory address 1F00
- (d)
at the memory address 2000
In an 8085 microprocessor based system, it is desired to increment the contents of memory location whose address is available in (DE) (register pair and store the result in the same location). The sequence of instruction is
- (a)
XCHG
INRM - (b)
SCHG
INRM - (c)
INX D
XCHG - (d)
INR M
XCHG
The contents (in Hexadecimal) of some of the memory locations in an 8085 A based system are given below.
Address | Contents |
---|---|
... | ... |
26FE | 00 |
26FF | 01 |
2700 | 02 |
2701 | 03 |
2702 | 04 |
... | ... |
The contents of Stack Pointer (SP), Program Counter (PC) and (H L) are 2700 H, 2100 Hand 0000 H respectively. When the following sequence of instructions are executed:
2100 H: DAD SP
2101 H: PCHL
The contents of SP and PC at the end of execution will be
- (a)
(PC)= 2102 H, (SP)= 2700 H
- (b)
(PC)= 2700 H, (SP)= 2700 H
- (c)
(PC)= 2800 H, (SP)= 26 FEH
- (d)
(PC)= 2A02H,(SP)= 2702H
Consider the following 8085 \(\mu P\) assembly program:
Line No. | Mnemonics | |
---|---|---|
1. | LXI | SP, 0400 H |
2. | LXI | B, 2055 H |
3. | LXI | H, 22FFH |
4. | LXI | D, 2090H |
5. | PUSH | H |
6. | PUSH | B |
7. | MOV | A, L |
.............. | ||
.............. | ||
.............. | ||
.............. | ||
20. | POP | H |
The memory location of the stack, where the first data byte will be stored is
- (a)
0399H
- (b)
0400H
- (c)
03FFH
- (d)
0401H
Consider an 8085 microprocessor system:
The following program starts at location 0100 H.
LXI SP, 00FF
LXI H, 0107
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109 H is
- (a)
20 H
- (b)
02 H
- (c)
00 H
- (d)
FF H