Electronics and Communication Engineering - Digital Electronics
Exam Duration: 45 Mins Total Questions : 30
Consider the following signed binary number A=01101101 and B=10110110, where B is the 1's complement and MSB is the sign bit.In list I operation is given and in List II resultant binary number is given and find the correct answer using the codes given below the lists
List I | List II |
---|---|
P.A+B | 1.00100100 |
Q.A-B | 2.01001001 |
R.B-A | 3.11001001 |
S.-A-B | 4.00100011 |
5.11011011 | |
6.10110110 | |
7.00100100 | |
8.01001000 |
- (a)
P Q R S 3 6 8 7 - (b)
P Q R S 1 6 2 5 - (c)
P Q R S 3 4 2 5 - (d)
P Q R S 1 4 8 7
The Boolean function f implemented in the figure using two input multiplexers is
- (a)
\(A\overset { - }{ B } C\)
- (b)
\(ABC+A\overset { - }{ B } \overset { - }{ C } \)
- (c)
\(\overset { - }{ A } BC\)
- (d)
\(\overset { - }{ A } \overset { - }{ B } C+\overset { - }{ A } B\overset { - }{ C } \)
Which of the following circuit represents a subtractor to subtract A from B?
- (a)
- (b)
- (c)
- (d)
None of these
A 2 digit BCD D/A converter is a weighted resistor type with \(V_{ R }=1V,R=1\quad m\Omega ,R_{ 1 }=10\quad k\Omega \) Resolution in per cent will be
- (a)
1%
- (b)
2%
- (c)
0.1%
- (d)
0.2%
An or GATE has 6 inputs. How many input words are there in its truth table?
- (a)
6
- (b)
36
- (c)
64
- (d)
64000
The circuit shown in given figure is a
- (a)
Positive logic OR circuit
- (b)
negative logic OR circuit
- (c)
positive logic NAND circuit
- (d)
negative logic NAND circuit
A 4-bit right shift register is initialized to value 1000 for Q3, Q2, Q1, Q 0 The 0 input is derived from Q 0,Q2 and Q3 through two XOR gates as shown in figure. The pattern 1000 will appear at
- (a)
3rd pulse
- (b)
7th pulse
- (c)
6th pulse
- (d)
4th pulse
In the following circuit, X is given by
- (a)
\(X=A\overline { B } C+\overline { A } \overline { B } C+ABC\)
- (b)
\(X=\overline { A } BC+A\overline { B } C+AB\overline { C } +\overline { A } \overline { B } \overline { C } \)
- (c)
X=AB+BC+AC
- (d)
\(X=\overline { A } \overline { B } +\overline { B } \overline { C } +\overline { A } \overline { C } \)
A 12 bit (32 digit) DAC that uses the BCD input code has a full scale output of 9.99 V The value of \(V_{ out }\) for in input code of 011010010101is
- (a)
4.11 V
- (b)
6.95 V
- (c)
7.38 V
- (d)
7.88 V
f=?
- (a)
\(\overline { W } X\overline { Y } \overline { Z } +W\overline { X } \overline { Y } \overline { Z } +XY+YZ\)
- (b)
\(W\overline { X } YZ+\overline { W } XYZ+\overline { X } \overline { Y } +\overline { Y } \overline { Z } \)
- (c)
\(W\overline { X } \overline { Y } \overline { Z } +\overline { W } \overline { X } \overline { Y } Z+Y\overline { Z } +ZX\)
- (d)
\(\overline { W } XYZ+WXY\overline { Z } +GZ+\overline { ZX } \)
The three-stage Johnson counter as shown in figure is clocked at a constant frequency of t. from the starting state of Q2Q1Q0 =101. The frequency of output Q2Q1Q0 will be
- (a)
fc/4
- (b)
fc/8
- (c)
fc/2
- (d)
fc/6
The minimum Boolean for the following circuit is
- (a)
AB+AC+BC
- (b)
AB+BC
- (c)
ABC+AC
- (d)
ABC
What are the counting stages (Q1, Q2) for the counter shown in the figure below?
- (a)
11, 10, 00, 1, 10 ...
- (b)
01, 10, 11, 00, 01, ...
- (c)
00, 11, 01, 10, 00,...
- (d)
01, 10, 00, 01, 10, ...
Given that for a logic family
VOH is minimum output high-level voltage
VOL is maximum output low-level voltage
VIH is minimum acceptable Input high-level voltage
VIL is maximum acceptable Input low-level voltage
The correct relationship is
- (a)
\(V_{ IH }>V_{ OH }>V_{ IL }>V_{ OL }\)
- (b)
\(V_{ OH }>V_{ IH }>V_{ IL }>V_{ OL }\)
- (c)
\(V_{ IH }>V_{ OH }>V_{ OL }>V_{ IL }\)
- (d)
\(V_{ OH }>V_{ IH }>V_{ OL }>V_{ IL }\)
Without any additional circuitry a 8 : 1 MUX can be used to obtain
- (a)
some but not all Boolean functions of 3 variables
- (b)
all functions of 3 variables but none of 4 variables
- (c)
all functions of 3 variables and some but not all of 4 variables
- (d)
all functions of 4 variables
The 4-to-1 multiplexer shown in figure implements the Boolean expression
f(w, x, y, z) = ∑m(4,5, 7,8,10,12,15)
The input to I1 and I3 will be
- (a)
\(Y\overline { Z } ,\overline { Y } +\overline { Z } \)
- (b)
\(\overline { Y } +Z,Y\bigodot Z\)
- (c)
\(\overline { Y } +Z,Y\oplus Z\)
- (d)
\(X+\overline { Y } ,Y\oplus Z\)
For MOD-12 counter the flip-flop has a \(t_{ pd }\)=60 ns The NAND gate has a \(t_{ pd }\) of 25 ns The maximum clock frequency is given by
- (a)
37.74 MHZ
- (b)
377.4 MHZ
- (c)
3.774 MHZ
- (d)
None of these
A master slave flip-flop has the characteristic that
- (a)
Change in the input immediately reflected in the output
- (b)
change in the output occurs when the state of the master is affected
- (c)
change in the output occurs when the state of the slave is affected
- (d)
both the master and the slave states are affected at the same time.
Wired logic is not possible in
- (a)
ECL
- (b)
TTL with active pull-up
- (c)
open-collector TTL
- (d)
TTL with passive pull-up
The MUX shown in figure is 4 x 1 multiplexer. The output Z is
- (a)
ABC
- (b)
\(A\oplus B\oplus C\)
- (c)
\(A\bigodot B\bigodot C\)
- (d)
A+B+C
A MUX network is shown in figure .
Z2=?
- (a)
ab+bc+ca
- (b)
a+b+c
- (c)
abc
- (d)
\(a\odot b\odot c\)
Consider the resistor transistor logic gate of figure
For negative logic the gate is
- (a)
AND
- (b)
OR
- (c)
NAND
- (d)
NOR
Consider the DL circuit of figure
For negative logic, the circuit is a
- (a)
AND
- (b)
OR
- (c)
NAND
- (d)
NOR
A PLA realization is shown in figure
\({ f }_{ 1 }\left( { x }_{ 2 },{ x }_{ 1 },{ x }_{ 0 } \right) =?\)
- (a)
\({ x }_{ 2 }\overline { { x }_{ 0 } } +{ x }_{ 1 }{ x }_{ 0 }\)
- (b)
\({ x }_{ 2 }{ x }_{ 0 }+{ x }_{ 1 }\overline { { x }_{ 2 } } \)
- (c)
\({ x }_{ 2 }\oplus { x }_{ 0 }\)
- (d)
\({ x }_{ 2 }\odot { x }_{ 0 }\)
The switching function f(A,B,C,D)=\(\sum { m } \) (5,9,11,14) can be written as
- (a)
\(A^{ ' }BC^{ ' }D+AB^{ ' }C^{ ' }D+AB^{ ' }CD+ABCD^{ ' }\)
- (b)
\(A^{ ' }BC^{ ' }D+AB^{ ' }C^{ ' }D+A^{ ' }B^{ ' }CD+ABCD^{ ' }\)
- (c)
\(A^{ ' }BC^{ ' }D+ABC^{ ' }D+AB^{ ' }CD^{ ' }+ABCD^{ ' }\)
- (d)
None of above
Choose the correct statement from the following
- (a)
PROM contains a programmable AND array and a fixed OR array
- (b)
PLA contains a fixed AND array and a programmable OR array
- (c)
PROM contains a fixed AND array and programmable OR array
- (d)
None of the above
The maximum positive and negative numbers which can be represented in 2's complememnt form using n-bit respectively
- (a)
\(+(2^{ n-1 }-1),-(2^{ n-1 }-1)\)
- (b)
\(+(2^{ n-1 }-1),-2^{ n-1 }-1\)
- (c)
\(+2^{ n-1 }-1,-2^{ n-1 }-1\)
- (d)
\(+2^{ n-1 }-1,-(2^{ n-1 }-1)\)
Below circuit of gate in (RTL) resistor transistor logic family. The circuit represents
- (a)
NAND
- (b)
AND
- (c)
NOR
- (d)
OR
Find \(f(x_{ 2 },x_{ 1 },x_{ 0 })=f\)
- (a)
\(\pi \) (1,2,4,5,7)
- (b)
\(\sum { (1,2,4,5,7) } \)
- (c)
\(\sum { (0,3,6) } \)
- (d)
None of these
A 10-bit D/A converter provides an analog output which has a maximum value of 10.23 V, The resolution is
- (a)
10 mV
- (b)
20 mV
- (c)
15 mV
- (d)
25 mV