Electronics and Communication Engineering - Microprocessors
Exam Duration: 45 Mins Total Questions : 30
An 8085 J..lPexecutes the following instructions
2710 LXIH, 30 AOH
2713 DAD H
2714 PCHL
All addresses and contents are in Hex. Let PC be the contents of the program counter and HL be contents of the HL register pair just after executing PCHL. Which of the following statements is correct?
- (a)
PC = 2715 H
HL = 30AOH - (b)
PC = 30AOH
HL=2715H - (c)
PC = 6140 H
HL = 6140 H - (d)
PC = 6140 H
HL = 2715 H
Which one of the following is not a vectored interrupt?
- (a)
TRAP
- (b)
INTR
- (c)
RST3
- (d)
RST 7.5
Match List I (Pre-terminals) with List II (Applications) and select the correct answer using the codes given below the lists.
| List I | List II |
| A. SID, SOD | 1. Wait state |
| B. Ready | 2. Interrupt |
| C. TRAP | 3. Serial data transfer |
| D. ALE | 4. Memory or I/O read/write |
| 5. Address latch control |
- (a)
A B C D 3 1 5 2 - (b)
A B C D 3 1 2 5 - (c)
A B C D 4 3 2 5 - (d)
A B C D 4 3 1 2
In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result
- (a)
carry flag will be set but zero flag will be reset
- (b)
carry flag will be reset but zero flag will be set
- (c)
both carry flag and zero flag will be reset
- (d)
both carry flag and zero flag will be set
Consider the following set of 8085 instructions:
MVI A, 8EH
ADI 73 H
JC DSPLY
OUT PORT 1
HLT
DSPLY: XRA A
OUT PORT1
HLT
The output at PORTl is
- (a)
00
- (b)
FEH
- (c)
01H
- (d)
11H
Consider the following ng 8085 assembly program:
MVI A, DATA1
MDV B, A
SUI 51H
JC DLT
MOV A, B
SUI 82H
JC DSPLY
DLT: XRA A
OUT PORT1
HLT
DLT: MOV
OUT
HLT
This program will display
- (a)
the bytes from 51H to 82H at PORT2
- (b)
00H AT PORT1
- (c)
all bytes at PORT1
- (d)
the bytes from 52H to 81 Hat PORT2
In a microprocessor, the register which holds the address of the next instruction to be fetched is
- (a)
accumulator
- (b)
program counter
- (c)
stack pointer
- (d)
instruction registers
When a CPU is interrupted, it
- (a)
stops execution of instructions
- (b)
acknowledge interrupt and branches subroutines
- (c)
acknowledge interrupt and continues
- (d)
acknowledge interrupt and waits for the next instruction from the interrupting device
Consider the sequence of 8085 instruction given below:
LXI H,9258H
MOV A, M
CMA
MOV M, A
By this sequence of instruction, the contents of memory location
- (a)
9258H are moved to the accumulator
- (b)
9258H are compared with the contents of the accumulator
- (c)
8529H are complemented and stored at location 529H
- (d)
5829H are complemented and stored at location 85892H
A OMA transfer implies
- (a)
direct transfer of data between memory and accumulator
- (b)
direct transfer of data between memory and input devices without use of microprocessor
- (c)
transfer of data exclusively within microprocessor register
- (d)
a fast transfer of data between microprocessor and input device
Consider the sequence of 8085 instruction
MVI A,5EH
AOI A2H
MOV C, A
HLT
The initial contents of register and flag are as follows
| A | C | S | Z | Y |
| xx | xx | 0 | 0 | 0 |
After execution of the instructions, the contents of register and flags are
- (a)
A C S Z CY 10H 10H 0 0 1 - (b)
A C S Z CY 10H 10H 1 0 0 - (c)
A C S Z CY 00H 00H 1 1 0 - (d)
A C S Z CY 00H 00H 0 1 1
The total number of memory accesses involved (including of the op-code fetch) when an 8085 microprocessor executes the instruction LDA 2003 is
- (a)
1
- (b)
2
- (c)
3
- (d)
4
Consider the following 8085 program:
MVI A, DATA1
ORA A,
JM DSPLY
OUT DSPLY
OUT PORT1
CMA
DSPLY: ADI 01H
OUT PORT1
HLT
If DATA 1 = A7H, the output at PORT1 is
- (a)
47H
- (b)
58H
- (c)
00
- (d)
None of these
Match the following while data moving between registers of the 8085 and the stack
| List I | List II |
| A. A PUSH instruction | 1. Pre-increment the stack pointer |
| B. A POP instruction | 2. Post-increments the stack pointer |
| 3. Pre-decrement of SP | |
| 4. Post-decrement of SP |
- (a)
A B
1 4 - (b)
A B
4 2 - (c)
A B
3 2 - (d)
A B
2 4
Consider the following loop:
XRA A
LXI B,0007H
LOOP: DCX B
JNZ LOOP
This loop will be executed
- (a)
1 times
- (b)
8 times
- (c)
7 times
- (d)
infinite times
An instruction used to set the carry the most computer can be classified as
- (a)
data transfer
- (b)
arithmetic
- (c)
logical
- (d)
memory control
In the 8085 microprocessor, the RST 6 instructions transfer the program execution to the location
- (a)
30
- (b)
24H
- (c)
48H
- (d)
60H
Consider the following set of instruction:
MVI A, BYTE1
RLC
MOV B, A
RLC
RLC
ADD B
If BYTE1 = 07H, then content of A after the execution of program wi II be
- (a)
46H
- (b)
70H
- (c)
38H
- (d)
68H
Consider the following program:
MVI A, BYTE1
RRC
RRC
If BYTE1 = 32H the contents of A after the execution of program will be
- (a)
08H
- (b)
8CH
- (c)
12H
- (d)
None of these
Consider the following instruction to be executed by an 80851lP. The input port has an address of 01 H and has a data 05H to input
IN 01H
ANI 80H
After execution of the two instructions, the contents of flag register are
- (a)
1 0 x 1 x 1 x 0
- (b)
0 1 x 0 x 1 x 0
- (c)
0 1 x 1 x 1 x 0
- (d)
0 1 x 1 x 0 x 0
Consider the execution of the following instruction by 8085 \(\mu P\)
MVI H, 01 FFH
SHLD 2050H
After execution the contents of memory, locations 2050H, 2051 H and registers H, L wi II be respectively
- (a)
01 H, FFH, FFH, 01 H
- (b)
FFH, 01 H, FEH, 01 H
- (c)
FFH, 01 H, 01 H, FFH
- (d)
01 H, FFH, 01 H, FFH
An 8085μP based system drives a multiplexed 5-digits 7-segment display. The digits are refreshed at a rate of 500 Hz. The On time for each digit is
- (a)
4 ms
- (b)
0.4 ms
- (c)
10 ms
- (d)
25 ms
The following program is run on 8085 microprocessor
| Memory add in Hex | Instruction |
|---|---|
| 1. 2000 | LXI SP, 1000 |
| 2. 2003 | PUSH H |
| 3. 2004 | PUSH D |
| 4. 2005 | CALL 2050 |
| 5. 2008 | POP H |
| 6. 2009 | HLT |
At the completion of step 4 execution of program the PC of 8085 contents and SP content will be respectively
- (a)
2050 H, 0FFAH
- (b)
2008 H, 0FFH
- (c)
2009 H, 1000H
- (d)
20009H, 0FFFCH
Consider the following set of 8085 instruction:
MVI A, DATAl
ORA A
JP DSPLY
XRA A
DSPLY : OUT PORT1
HLT
If DATA1 = 92H, the output at PORT1 is
- (a)
00
- (b)
FFH
- (c)
92H
- (d)
None of these
An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped, I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its three ports and the control register. The address lines A3 to A7 as well as the 10/M signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is
- (a)
F8H-FBH
- (b)
F8H-FCH
- (c)
F8H-FFH
- (d)
F0H-F7H
If \((\overline { CS } )=\overline { A_{ 15 } } \)= A14 A13 is used as Chip Select logic of a 4 k RAM in an 8085 system. Then its memory range will be
- (a)
3000 H - 3FFFH
- (b)
7000 H - 7FFFH
- (c)
5000 H - 5FFFH and 6000 H - 6FFFH
- (d)
6000 H - 6FFFH and 7000 H - 7FFFH
Consider the following 8085 μP assembly program:
| Line No. | Mnemonics | |
|---|---|---|
| 1. | LXI | Sp,0400 H |
| 2. | LXI | B, 2055 H |
| 3. | LXI | H, 22FFH |
| 4. | LXI | D,2090H |
| 5. | PUSH | H |
| 6. | PUSH | B |
| 7. | MOV | A, L |
| ............ | ||
| ............ | ||
| ............ | ||
| ............ | ||
| 20. | POP | H |
When line 5 is executed, the contents of memory location 03FEH will be
- (a)
FFH
- (b)
22H
- (c)
20H
- (d)
90H
Consider an 8085 microprocessor system:
The following program starts at location 0100 H.
LXI SP, 00FF
LXI H, 0107
MVI A, 20H
SUBM
The content of accumulator when the program counter reaches 0109 H is
- (a)
20 H
- (b)
02 H
- (c)
00 H
- (d)
FFH
Consider an 8085 microprocessor system:
If in addition, following code exists from 0109 H onwards.
ORI 40H
ADD M
What will be the result in the accumulator after the last instruction is executed?
- (a)
40 H
- (b)
20 H
- (c)
60 H
- (d)
42 H
Consider the following program of 8085 assembly language:
LXI H 4A02H
LDA 4A00H
MOV B, A
LDA 4A01H
CMP B
JZ FNSH
JC GRT
MOV M, A
JMP FNSH
MOV M, B
FNSH: HLT
If the contents of memory locations 4A00H, 4A01 H and 4A02H are, respectively A7H, 98H, and 47H then, after the execution of program, contents of memory location 4A02H will be
- (a)
A7H
- (b)
98H
- (c)
47H
- (d)
None of these
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